1. Field of the Invention
The present invention relates to mechanisms for assessing damage caused by an error in computer systems; and more particularly to systems for tracing the impact of an error on a data processing unit within a large scale computer system.
2. Description of Related Art
In large scale computer systems, such as those operating in accordance with the IBM ESA/390 architecture, the impact of an error is frequently determined by the state of the machine when the error occurred. Prior art machines use hardware to assess the severity of a particular error. Thus, error detection logic is distributed in prior art machines which detects and signals a service processor through a scan facility or otherwise of the occurrence of the error, and of the classification for the error based on the state of the machine when the error occurred. The service processor coupled to the scan facility, is then capable of taking an appropriate response.
Use of hardware to assess the damage caused by an error suffers many disadvantages. In particular, the hardware must be designed in advance based on a prediction of the types of errors that may occur. Thus, the hardware may not include information that could be critical to assessing the damage caused by an error that may be considered unlikely when the machine is designed. Also, the hardware costs of logic incorporating all important machine state information are quite high in complex machines.
Accordingly, it is desirable to provide a mechanism for assessing damage caused by an error, that provides more flexibility and less hardware costs.